1. Field of the Invention
The present invention relates to a frame synchronizer designed to synchronize serial digital data in which video data and audio data are multiplexed onto each other to a reference signal of the self system and to output the data.
2. Description of the Related Art
Hitherto, there is a frame synchronizer of the known art which synchronizes audio visual serial digital interface (AV-SDI) data in which audio data and video data from another system are multiplexed onto each other to a reference signal of the self system and which outputs the data.
The operation of such a frame synchronizer will now be described with reference to FIG. 3B. As shown in FIG. 3B, serial input data AV-SDI In, shown in (a) of FIG. 3A, in which audio data and video data from another system are multiplexed onto each other, and a reference signal Ref, shown in (b) of FIG. 3A, of the self system are input to an SDI frame synchronizer (AV frame synchronizer) 100. The frame synchronizer 100 synchronizes the serial input data AV-SDI In to the reference signal Ref as shown at (c) of FIG. 3A and outputs it as serial output data AV-SDI Out.
Figures (d) to (f) of FIG. 3A show the states in which parts of the signals shown at (a) to (c) of FIG. 3A are expanded. The serial input data AV-SDI In and the serial output data AV-SDI Out are assumed to be digital data in which audio data and video data are multiplexed onto each other; however, they are shown in an analog form, and the reference signal Ref is assumed to be an analog video signal. It can be seen in these figures that the serial input data AV-SDI In which is out of synchronization is assumed to be the serial output data AV-SDI Out which is in synchronization with the reference signal Ref.
An example of the arrangement of such a frame synchronizer 100 is shown in FIG. 4. In FIG. 4, serial digital data SDI (Serial Digital Interface) in which audio data and video data are multiplexed onto each other is input to the frame synchronizer 100 wherein the data is converted into parallel data by a serial/parallel conversion circuit 101. This parallel data is supplied to a frame memory (FSY) 102 and a timing detection circuit (Timing DET) 103.
The timing detection circuit 103 detects the timing of the digital data which has been converted into parallel data and outputs a timing signal based on the detected timing to a write control circuit (Write Control) 104.
The write control circuit 104 forms a write control signal, such as address data or an enable signal, at the timing of the supplied timing signal and controls the writing in the frame memory 102 in accordance with this write control signal. In this way, the input digital data AV-SDI is written in the frame memory 102 in accordance with its own timing.
Further, the reference signal Ref is input to a synchronization separation circuit (Sy Sep) 105 wherein the signal is separated into a horizontal synchronization signal and a vertical synchronization signal, and the separated synchronization signals are supplied to a read control circuit (Read Control) 106.
The read control circuit 106 forms a read control signal, such as address data or an enable signal, in accordance with the supplied synchronization signal and controls the reading from the frame memory 102 in accordance with the read control signal. More specifically, digital data in which audio data and video data are multiplexed onto each other is read from the frame memory 102 at the timing of the input reference signal Ref, and thus, the digital data is synchronized with the reference signal Ref.
Then, the digital data, in which audio data and video data are multiplexed onto each other, read from the frame memory 102 is separated into video data and audio data by a video/audio separation (A/V Sep) circuit 107. The separated video data is processed by a video processing (V Proc) section 109, and the processes for synchronizing the separated audio data to the video data are performed by an audio processing section (A Proc) 108. The video data and audio data are supplied to an audio/video multiplexer (AVM) 110.
Further, the multiplexed digital data output from the audio/video multiplexer 110 is converted into serial data by a parallel/serial conversion circuit (PS) 111 and output as serial digital data SDI.
As described above, by assuming the writing in the frame memory 102 to be the timing of the input digital data and the reading from the frame memory 102 to be the timing of the reference signal Ref, the SDI frame synchronizer 100 outputs the serial digital data SDI in which audio data and video data are multiplexed onto each other in synchronization with the reference signal Ref.
An example of the arrangement of a conventional AV frame synchronizer of an NTSC (National Television System Committee) system, to which analog audio and video signals are input, is shown in the block diagram of FIG. 5. The AV frame synchronizer comprises a frame synchronizer section 200 and an audio delay line section 300.
In the frame synchronizer section 200 shown in FIG. 5, an input analog NTSC video signal is converted into a digital video signal by an analog/digital converter (ADC) 201 and supplied to a frame memory (FSY) 202. Further, the input analog NTSC video signal is input to a write clock generation circuit (WCk Gen) 203 where a write clock based on the timing of the horizontal synchronization signal and the vertical synchronization signal thereof is generated and supplied to the ADC 201 and the frame memory 202.
Thereupon, the input analog NTSC video signal is converted into a digital signal at the write clock timing by the ADC 201 and written in the frame memory 202 at the write clock timing.
Further, an analog reference signal Analog Ref has been input to the frame synchronizer section 200. This analog reference signal Analog Ref is input to a read clock generation circuit (RCk Gen) 205 where a read clock based on the timing of the input is generated and supplied to the frame memory 202. Thereupon, the digital NTSC video data stored in the frame memory 202 is read out at the read clock timing and supplied to a digital/analog converter (DAC) 206.
The read clock generated from the read clock generation circuit has been supplied to the DAC 206. In the DAC 206, digital data read out from the frame memory 202 is converted into an analog signal at this read clock timing and this converted analog NTSC video signal is output. As a result, the output analog NTSC video signal is synchronized with the analog reference signal Analog Ref.
Further, the timing signal output from the write clock conversion circuit 203 and the timing signal output from the read clock conversion circuit 205 are input to a synchronization timing detection circuit (Sy Timing Detection) 204 where the phase difference between the two timing signals is detected. This phase difference corresponds to the phase difference between the input analog NTSC video signal and the analog reference signal Analog Ref.
On the other hand, the analog audio signal is input to the audio delay line section 300 and is converted into digital audio data by an ADC 301. This digital audio data is input to a digital delay line (Delay) 302 controlled by a delay control circuit (DELAY CTL) 305 whereby it is delayed a predetermined amount, and the digital audio data is converted into analog audio data and output by the DAC 304.
At this point, the phase difference signal detected by the synchronization timing detection circuit 204 is supplied to a digital delay line 302, with the result that because the amount of delay of the digital delay line 302 is controlled, the digital audio data output from the audio delay line section 300 is synchronized with the analog NTSC video signal output from the frame synchronizer section 200.
Further, an audio clock ACk generated by an audio clock generator (ACk Gen) 303 is supplied to the ADC 301, the digital delay line 302 and the DAC 304, which operate at the timing of the audio clock ACk.
According to the AV frame synchronizer shown in FIG. 5, the analog NTSC video signal is output in synchronization with the analog reference signal Analog Ref by the frame synchronizer section 200, and the analog audio signal is output in synchronization with the analog NTSC video signal by the audio delay line section 300.
In the conventional SDI synchronizer, since the frequency of the SDI data input from another system is generally different from that of the reference signal Ref of the self system, there is a case in which a writing signal of the frame memory and a reading signal of the frame memory come close to each other and thus, enter a prohibition area. Since, in such cases, the operation becomes unstable, the reading timing of the frame memory is made to jump one field or one frame ahead so that the writing signal and reading signal of the frame memory do not enter the operation undetermined area.
However, if the reading timing of the frame memory is made to jump one field or one frame ahead, audio data multiplexed on a video tape is also made to jump to one field or one frame ahead.
If so, the continuity of the audio data is disrupted, causing a problem where a click noise is generated in audio signals. The magnitude of this click noise is determined on the basis of the connected state of audio data before and after the noncontinuous point, that is, the phase state. There are cases in which a large noise occurs, and cases in which a noise of a low magnitude such as to not cause disturbance occurs, and cases in which the magnitude of noise is non-uniform.
The frame jump due to the difference in system frequencies occurs at the following interval in the worst case when, for example, the sampling frequency of the NTSC system differs by .+-.10 Hz: EQU (910.times.525)/(4.times.20.times.3600).apprxeq.1.66 hours!.
When the sampling frequency of the PAL (Phase Alteration by Line) system differs by .+-.1 Hz, the frame jump occurs at the following interval in the worst case: EQU (1135.times.625)/(4.times.2.times.3600).apprxeq.24.63 hours!
causing a click noise to occur at each time thereof.